Instead of editing the .hex file as suggested in the README.TXT we can use this approach:
$ dd if=/dev/zero of=pad2mb.bin bs=1024 count=2048
$ cat nuttx.bin pad2mb.bin > nuttxpad.bin
$ dd if=nuttxpad.bin of=nuttxpad2mb.bin bs=1024 count=2048
$ cat nuttxpad2mb.bin nuttx_user.bin > nuttxfinal.bin
If you want to start your application on NuttX directly without using the NSH you can setup your “app_main” in the ENTRYPOINT, although you will see that some drivers will not start anymore.
You can fix it enabling the “Board Late Init” in the menuconfig:
RTOS Features ---> RTOS hooks ---> [*] Custom board late initialization
Also you need to disable the architecture-specific initialization:
Application Configuration ---> NSH Library ---> Have architecture-specific initialization
I was looking for a way to align registers definitions like these:
#define REGISTER_XYZ 0x0001
#define REGISTER_A 0x0002
…
And I found this nice tip:
qa -- Record a macro in hotkey a 0 -- Go to the beginning of the line f= -- Go to the first equals sign 100i <Esc> -- (There's a single space after the i, and the <Esc> means press escape, don't type "<Esc>".) Insert 100 spaces 8| -- Go to the 8th column (sorry, you'll have to manually figure out which column to align to) dw -- Delete until the next non-space character j -- Go to the next line q -- Stop recording.
In my case I just replaced the “f=” with “f0” and “8|” with “33|”
Found SW-DP with ID 0x2BA01477
Unknown DP version. Assuming DPv0
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x24770011)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
Found Cortex-M4 r0p1, Little endian.
FPUnit: 6 code (BP) slots and 2 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
Cortex-M4 identified.
J-Link>loadbin nuttx.bin, 0
Halting CPU for downloading file.
Downloading file [nuttx.bin]…
Writing target memory failed.
J-Link>erase
Erasing device…
J-Link: Flash download: Only internal flash banks will be erased.
To enable erasing of other flash banks like QSPI or CFI, it needs to be enabled via "exec EnableEraseAllFlashBanks"
Erasing flash [100%] Done.
Error: Failed to erase chip @ address 0x08000000 (Algo87: Unspecified error #1)
Failed to erase chip.
Failed to execute RAMCode for chip erase!
J-Link: Flash download: Total time needed: 0.105s (Prepare: 0.064s, Compare: 0.000s, Erase: 0.001s, Program: 0.000s, Verify: 0.000s, Restore: 0.038s)
ERROR: Erase returned with error code -5.
J-Link>
Strange, after resetting the board and writing a .hex instead of a .bin worked…
I was trying to run NuttX RTOS on iMXRT1060_EVK board (it has an
external 8MiB QSPI Flash), but because my JLink EDU is version V8 it
doesn’t supports Cortex-M7.
Using the DAPLink drag-and-drop I can copy small nuttx firmwares
(i.e.: up to 73KB worked), but when I compile NuttX to PROTECTED Mode
it doesn’t work. Because the kernel is at the beginning of the flash
and the userspace is at offset +2MB. Then during the copy it reports
timeout.
Then I tried to use OpenOCD. I got it working for debugging, but it
doesn’t have support to flash the QSPI for NXP chips, only for
STMicro.
While searching for a solution I found this post:
https://community.nxp.com/thread/518836
“You can actually run the LPC-Link2 firmware on the onboard debug
probe of the RT1064-EVK board, in place of the default DAP-Link
firmware. For more details see:”
That points to this post:
https://community.nxp.com/community/mcuxpresso/mcuxpresso-ide/blog/2019/01/23/overview-of-using-the-mimxrt1060-evk-with-mcuxpresso-ide
Reading this PDF I discovered that if I wire the jumper J42 near the
LPC4322, the firmware will work as a native LPC-Link2, instead of a
DAPLink.
It is strange because in the User’s Guide there is nothing about this
jumper: https://www.avnet.com/opasdata/d120001/medias/docus/192/NXP-MIMXRT1060-EVK-User-Guide.PDF
And in fact it works as DFU mode:
[ 638.833516] usb 1-1: new high-speed USB device number 9 using xhci_hcd
[ 638.982422] usb 1-1: New USB device found, idVendor=1fc9,
idProduct=000c, bcdDevice= 1.00
[ 638.982428] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 638.982434] usb 1-1: Product: LPC
[ 638.982436] usb 1-1: Manufacturer: NXP
[ 638.982439] usb 1-1: SerialNumber: ABCD
$ sudo dfu-util -d 0x1fc9:0x000c -l
dfu-util 0.9
…
Found DFU: [1fc9:000c] ver=0100, devnum=9, cfg=1, intf=0, path="1-1",
alt=0, name="DFU", serial="ABCD"
But I need to find the .hdr file to implement the LPCScrypt for this
iMXRT1060 chip, like I did some time ago for LPC43:
https://acassis.wordpress.com/2017/03/28/using-lpcscrypt-to-flash-firmware-on-bambino-board/
I have a LPCXpresso54628 board here, then I thought about the idea of
using its LPC-Link2 to program the iMXRT1060. But that should be more complicated.
While searching for a solution I found this post:
https://community.nxp.com/thread/518836
“You can actually run the LPC-Link2 firmware on the onboard debug
probe of the RT1064-EVK board, in place of the default DAP-Link
firmware. For more details see:”
That points to this post:
https://community.nxp.com/community/mcuxpresso/mcuxpresso-ide/blog/2019/01/23/overview-of-using-the-mimxrt1060-evk-with-mcuxpresso-ide
Reading this PDF I discovered that if I wire the jumper J42 near the
LPC4322, the firmware will work as a native LPC-Link2, instead of a
DAPLink.
It is strange because in the User’s Guide there is nothing about this
jumper: https://www.avnet.com/opasdata/d120001/medias/docus/192/NXP-MIMXRT1060-EVK-User-Guide.PDF
I decided to document the steps needed to get the Low Power SPI working on iMXRT1050-EVKB and I hope it could be useful for other people using this board. But the basic idea apply to any other board supported by NuttX.
Everything starts with the schematic, you need to spot the SPI pins that you want to use and which SPI Port it belongs to.
Right, so we found the SPI pins and its MCU pins:
D10/SPI_CS -> GPIO_SD_B0_01
D11/OC2A/PWM/SPI_MOSI -> GPIO_SD_B0_02
D12/SPI_MISO -> GPIO_SD_B0_03
D13/SPI_CLK -> GPIO_SD_B0_00
Now we can find these pins definition on NuttX looking at the file arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h :
#define GPIO_LPSPI1_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) #define GPIO_LPSPI1_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) #define GPIO_LPSPI1_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) #define GPIO_LPSPI1_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
Perfect, but here you need to know an important information about NuttX: normally the NuttX SPI drivers don’t use the native CS (Chip Select) pin, instead it use ordinary GPIO pins to work as CS. The reason behind it is because normally the SPI Hardware has a limited number os HW CS pins (normally 4 pins). So instead of limiting the user to only 4 devices (CS), NuttX allow you to use how many CS pins as you wish.
Now we need to see in the LPSPI driver what is the name of pins it uses, so we will associate these pins to those from the pinmux header file.
Just open the file arch/arm/src/imxrt/imxrt_lpspi.c and search for imxrt_config_gpio(), this is the function used to configure the pins on iMXRT10xx chips.
imxrt_config_gpio(GPIO_LPSPI1_SCK); imxrt_config_gpio(GPIO_LPSPI1_MISO); imxrt_config_gpio(GPIO_LPSPI1_MOSI);
All we need to do is to point these pins to our SPI pins (that we found in the pinmux.h).
You can do it adding these line to boards/arm/imxrt/imxrt1050-evk/include/board.h file:
#define GPIO_LPSPI1_SCK (GPIO_LPSPI1_SCK_2|IOMUX_LPSPI_DEFAULT) #define GPIO_LPSPI1_MISO (GPIO_LPSPI1_SDI_2|IOMUX_LPSPI_DEFAULT) #define GPIO_LPSPI1_MOSI (GPIO_LPSPI1_SDO_2|IOMUX_LPSPI_DEFAULT)
Ok, but where is the the Chip Select pin?
Don’t worry, if you look at iMXRT1050 Datasheet you will see that this CS pin (GPIO_SD_B0_01) is the GPIO3.IO[13] and it is already defined at boards/arm/imxrt/imxrt1050-evk/src/imxrt1050-evk.h this way:
#define GPIO_LPSPI1_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \
GPIO_PORT3 | GPIO_PIN13 | IOMUX_LPSPI1_CS)
So, with the basic configuration in place, now we can start defining our SPI device initialization. Let me think what SPI device we could you. Well, since I want you to “see” the SPI working, let’s to use the MAX7219 7-segment numeric display! 
Fortunately we have the boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c as example to initialize our MAX7219 display.
We can copy it and modify to become an iMXRT file:
$ cp boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c boards/arm/imxrt/imxrt1050-evk/src/imxrt_max7219_leds.c
Replace all references to stm32f4discovery with imxrt1050-evk and all stm32 with imxrt!
You need to take care with some functions name replacement, ie:
stm32_spibus_initialize(MAX7219_SPI_PORTNO);
will become:
imxrt_lpspibus_initialize(MAX7219_SPI_PORTNO);
We are almost done, but we need to define this file to be compiled and we need to call its initialization function to register the display device.
To compile this file we just need to edit the file boards/arm/imxrt/imxrt1050-evk/src/Makefile and add these lines:
ifeq ($(CONFIG_LEDS_MAX7219),y)
CSRCS += imxrt_max7219_leds.c
endif
And to call the initialization we just add these lines to boards/arm/imxrt/imxrt1050-evk/src/imxrt_bringup.c inside imxrt_bringup() function:
#ifdef CONFIG_LEDS_MAX7219
ret = imxtrt_max7219init("/dev/numdisp0");
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: max7219_leds_register failed: %d\n", ret);
}
#endif
After everything is in place you can configure your iMXRT1050-EVK board, enter in the menuconfig and select:
System Type -> i.MX RT Peripheral Selection -> LPSPI Peripherals -> [*] LPSPI1
Device Drivers -> [*] SPI Driver Support
Device Drivers -> LED Support -> [*] MAX7219 Numeric Display
Save and Exit. Just type “make” to compile.
When the compilation finish you can look at the System.map file and search for max7219, you should see these symbols:
6000f954 T imxrt_max7219init
6000f974 t max7219_open
6000f978 t max7219_read
6000f97e t max7219_write16.isra.0
6000f9f4 t max7219_write
6000fb4e t max7219_close
6000fb52 T max7219_leds_register
Flash the firmware in the board (with SW7 1-off 2-on 3-on 4-off I just dropped the nuttx.hex in the disk), open the /dev/ttyACM0 and reset the board, you show see:
NuttShell (NSH) NuttX-9.1.0 nsh> uname -a NuttX 9.1.0 9a1391d36b-dirty Aug 8 2020 12:23:10 arm imxrt1050-evk nsh> ls /dev /dev: console null numdisp0 ttyS0 nsh>
As you can see our /dev/numdisp0 is there!
Note: you need to solder the resistors R281, R279, R278 and R280 to get LPSPI1 working.
I decided to test the SDCard support on iMXRT1050-EVK board, but go these errors:
CC: chip/imxrt_lowputc.c chip/imxrt_lowputc.c: In function 'imxrt_lpuart_configure': chip/imxrt_lowputc.c:559:2: warning: #warning missing logic [-Wcpp] 559 | #warning missing logic | ^ CC: chip/imxrt_idle.c CC: chip/imxrt_timerisr.c chip/imxrt_timerisr.c:63:2: warning: #warning REVISIT these clock settings [-Wcpp] 63 | #warning REVISIT these clock settings | ^ CC: chip/imxrt_usdhc.c chip/imxrt_usdhc.c:100:4: error: #error "CONFIG_SDIO_BLOCKSETUP is mandatory for this driver" 100 | # error "CONFIG_SDIO_BLOCKSETUP is mandatory for this driver" | ^ In file included from chip/imxrt_usdhc.c:60: chip/imxrt_usdhc.c: In function 'imxrt_usdhc_initialize': chip/imxrt_usdhc.c:3144:25: error: 'GPIO_USDHC1_DATA0' undeclared (first use in this function); did you mean 'GPIO_USDHC1_DATA0_1'? 3144 | imxrt_config_gpio(PIN_USDHC1_D0); | ^ chip/imxrt_usdhc.c:3144:25: note: each undeclared identifier is reported only once for each function it appears in chip/imxrt_usdhc.c:3145:25: error: 'GPIO_USDHC1_CLK' undeclared (first use in this function); did you mean 'GPIO_USDHC1_CLK_1'? 3145 | imxrt_config_gpio(PIN_USDHC1_DCLK); | ^ chip/imxrt_usdhc.c:3146:25: error: 'GPIO_USDHC1_CMD' undeclared (first use in this function); did you mean 'GPIO_USDHC1_CMD_1'? 3146 | imxrt_config_gpio(PIN_USDHC1_CMD); | ^ make[1]: *** [Makefile:151: imxrt_usdhc.o] Error 1
The first error as easy to fix: just run “make menuconfig” press the key “/” and search for “CONFIG_SDIO_BLOCKSETUP” you will find the:
Prompt: SDIO block setup
Just press 1 do go directly to it and then enable it:
[*] SDIO block setup
After trying to compile again you will see that the pins definition still missing: PIN_USDHC1_D0, PIN_USDHC1_DCLK, PIN_USDHC1_CMD. Just like we did for SPI in the previous post, you need to start looking the schematics.
First let see the SDCard slot:
So, let search for these pins: SD1_CLK, SD1_CMD, SD1_D0, SD1_D1, SD1_SD2, SD1_D3 and SD_CD_SW:
So, we have:
SD1_CMD = GPIO_SD_B0_00
SD1_CLK = GPIO_SD_B0_01
SD1_D0 = GPIO_SD_B0_02
SD1_D1 = GPIO_SD_B0_03
SD1_D2 = GPIO_SD_B0_04
SD1_D3 = GPIO_SD_B0_05
SD_CD_SW = GPIO_B1_12
And like we did for the SPI, let’s to look at arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h for these GPIO_SD_* pins definition:
#define GPIO_USDHC1_CMD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
#define GPIO_USDHC1_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
#define GPIO_USDHC1_DATA0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
#define GPIO_USDHC1_DATA1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX))
#define GPIO_USDHC1_DATA2_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
#define GPIO_USDHC1_DATA3_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
#define GPIO_GPIO2_IO28_1 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX))
So, we need to include the missing SD1 pins pointing to these defines names at boards/arm/imxrt/imxrt1050-evk/include/board.h this way:
/* MMC/SD SD1 */ #define PIN_USDHC1_DCLK GPIO_USDHC1_CLK_1 #define PIN_USDHC1_CMD GPIO_USDHC1_CMD_1 #define PIN_USDHC1_D0 GPIO_USDHC1_DATA0_1
Ok, after defining these pins the compilation finished correctly. But the fact of the USDHC driver is only failing because DATA0 rings a bell! Probably it is using SD Card with 1-bit interface, we need to enable 4-bits interface:
$ make menuconfig
System Type ->
USDHC Configuration ->
Bus width for USDHC1 (Four bit)
Perfect, now the compilation is failing, this is exactly what I was waiting for:
CC: chip/imxrt_usdhc.c
In file included from chip/imxrt_usdhc.c:60:
chip/imxrt_usdhc.c: In function 'imxrt_usdhc_initialize':
chip/imxrt_usdhc.c:3138:25: error: 'GPIO_USDHC1_DATA1' undeclared (first use in this function); did you mean 'GPIO_USDHC1_DATA2_1'?
3138 | imxrt_config_gpio(PIN_USDHC1_D1);
| ^
chip/imxrt_usdhc.c:3138:25: note: each undeclared identifier is reported only once for each function it appears in
chip/imxrt_usdhc.c:3139:25: error: 'GPIO_USDHC1_DATA2' undeclared (first use in this function); did you mean 'GPIO_USDHC1_DATA2_1'?
3139 | imxrt_config_gpio(PIN_USDHC1_D2);
| ^
chip/imxrt_usdhc.c:3140:25: error: 'GPIO_USDHC1_DATA3' undeclared (first use in this function); did you mean 'GPIO_USDHC1_DATA3_1'?
3140 | imxrt_config_gpio(PIN_USDHC1_D3);
| ^
make[1]: *** [Makefile:151: imxrt_usdhc.o] Error 1
make[1]: Leaving directory '/comum/workspace/Consultancy/iDTech/NuttX/nuttx/arch/arm/src'
make: *** [tools/LibTargets.mk:155: arch/arm/src/libarch.a] Error 2
You already know what to do, right? Just insert all the pins to board.h :
/* MMC/SD */
#define PIN_USDHC1_DCLK GPIO_USDHC1_CLK_1
#define PIN_USDHC1_CMD GPIO_USDHC1_CMD_1
#define PIN_USDHC1_D0 GPIO_USDHC1_DATA0_1
#define PIN_USDHC1_D1 GPIO_USDHC1_DATA1_1
#define PIN_USDHC1_D2 GPIO_USDHC1_DATA2_1
#define PIN_USDHC1_D3 GPIO_USDHC1_DATA3_1
Excellent! Now it is compiling with 4-bit SDCard interface.
But wait! What about the SDCard insertion pin (SD_CD_SW)? If you look at arch/arm/src/imxrt/imxrt_usdhc.c you will see that it is waiting for a pin named PIN_USDHC1_CD_GPIO, so let to declare it pointing to our pin:
#define PIN_USDHC1_CD_GPIO (IOMUX_VSD_DEFAULT | \
GPIO_PORT2 | GPIO_PIN28)
With everything in place, compile, flash, put a SDCard in the board’s slot and Voilà:
NuttShell (NSH) NuttX-9.1.0 nsh> uname -a NuttX 9.1.0 74c16e8d6d-dirty Aug 9 2020 12:58:00 arm imxrt1050-evk nsh> ls /dev /dev: console mmcsd0 null numdisp0 ttyS0 nsh> mount -t vfat /dev/mmcsd0 /mnt nsh> ls /mnt /mnt: LOST.DIR/ Android/ .android_secure/ nsh>
I was looking for a way to save all the emails returned after searching for some word.
There is not an direct way to do it, so this is a workaround:
Thanks user Dave Thompson 8260 for this tip: https://support.google.com/mail/thread/9010168?hl=en
This is the test suite used to verify the randomness of (True) RNG algorithms or hardware.
NuttX is evolving all the time and although I created a video tutorial at NuttX Channel explaining how to create a RAMDISK, that information is already outdated.
Let’s do it again using the current NuttX version (9.1)
First select the needed options at menuconfig:
Device Drivers --->
[*] RAM disk wrapper (mkrd)
Board Selection --->
[*] Enable boardctl() interface
[*] Enable application space creation of RAM disks
File Systems --->
[*] FAT file system
Compile it and run these commands when NuttX’s nsh show up on serial console:
NuttShell (NSH) NuttX-9.1.0 nsh> ? help usage: help [-v] [] . cd echo hexdump mkrd pwd test usleep [ cp exec kill mh rm time xd ? cmp exit ls mount rmdir true basename dirname false mb mv set uname break dd free mkdir mw sleep umount cat df help mkfatfs ps source unset Builtin Apps: sh nsh nsh> mkrd 64 nsh> ls /dev /dev: console null ram0 <--- ttyS0 nsh> mkfatfs /dev/ram0 nsh> mount -t vfat /dev/ram0 /mnt nsh> echo "This is a file in RAMDISK" > /mnt/file.txt nsh> cat /mnt/file.txt This is a file in RAMDISK nsh>
$ git clone https://github.com/spiriou/incubator-nuttx-apps apps
$ git clone https://github.com/apache/incubator-nuttx
$ cd apps
$ git checkout -b iotjs origin/iotjs
Branch 'iotjs' set up to track remote branch 'iotjs' from 'origin'.
Switched to a new branch 'iotjs'
$ cd ../incubator-nuttx
Config:
CONFIG_ARCH_FPU is not set
CONFIG_NSH_ARGCAT is not set
CONFIG_NSH_CMDOPT_HEXDUMP is not set
CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="stm32f4discovery"
CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_SETJMP_H=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LATE_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_INTELHEX_BINARY=y
CONFIG_IOTJS=y
CONFIG_LIBUV=y
CONFIG_LIBUV_FS=y
CONFIG_LIBUV_TCP=y
CONFIG_LIBUV_TIMER=y
CONFIG_LIBUV_WQ=y
CONFIG_MAX_TASKS=16
CONFIG_MM_REGIONS=2
CONFIG_NET=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_KEEPALIVE=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_USART2_RXBUFSIZE=128
CONFIG_USART2_SERIAL_CONSOLE=y
CONFIG_USART2_TXBUFSIZE=128
CONFIG_USER_ENTRYPOINT="nsh_main"
$ make
$ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg -c init -c "reset halt" -c "flash write_image erase nuttx.bin 0x08000000"
Create the RAMDISK:
nsh> mkrd 64
nsh> mkfatfs /dev/ram0
nsh> mount -t vfat /dev/ram0 /mnt
Create the sample file:
nsh> echo "var fs = require('fs');" > /mnt/index.js
nsh> echo "console.log('Hello World');" >> /mnt/index.js
Confirm it is correct:
nsh> cat /mnt/index.js
var fs = require('fs');
console.log('Hello World');
Is iotjs here?
nsh> ?
help usage: help [-v] []
. cd exec ifdown mkrd pwd time
[ cp exit ifup mh rm true
? cmp false kill mount rmdir uname
arp dirname free ls mv set umount
basename dd help mb mw sleep unset
break df hexdump mkdir nslookup source usleep
cat echo ifconfig mkfatfs ps test xd
Builtin Apps:
iotjs sh hello nsh
All right, run it:
nsh> iotjs /mnt/index.js
Hello World
nsh>
So you decided to create a project (board) and used a chip just a little bit different from the recommended in the datasheet, please don’t do it.
You can read the reasons here:
https://www.maximintegrated.com/en/design/technical-documents/tutorials/4/4429.html
This is common error on NuttX, but unfortunately the build system is not clear to explain to the user about it.
$ git clone https://github.com/apache/incubator-nuttx $ cd incubator-nuttx $ ./tools/configure.sh esp32-core:nsh ... This program built for x86_64-pc-linux-gnu Report bugs to bug-make@gnu.org make: *** [tools/Makefile.unix:319: dirlinks] Error 2 ERROR: failed to refresh
This problem happens because you missed to clone the apps/ repository:
$ cd ..
$ git clone https://github.com/apache/incubator-nuttx-apps apps
Now you can configure it correctly:
$ cd incubator-nuttx $ ./tools/configure.sh esp32-core:nsh ... # # configuration written to .config #
I’m using the Mi Earbuds for two days and these are my impressions so far:
So, I’m happy with this product, but I think Xiaomi could make improvements for the next models to fix these points.
rst:0x1 (POWERON_RESET),boot:0x1e (SPI_FAST_FLASH_BOOT) configsip: 0, SPIWP:0xee clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 mode:DIO, clock div:2 load:0x3fff0030,len:4 load:0x3fff0034,len:7160 load:0x40078000,len:13376 ho 0 tail 12 room 4 load:0x40080400,len:4084 entry 0x40080680 I (30) boot: ESP-IDF v4.2-dev-1883-gb8f5d2e46 2nd stage bootloader I (30) boot: compile time 17:37:10 I (30) boot: chip revision: 1 I (35) boot_comm: chip revision: 1, min. bootloader chip revision: 0 I (42) boot.esp32: SPI Speed : 40MHz I (46) boot.esp32: SPI Mode : DIO I (51) boot.esp32: SPI Flash Size : 2MB I (55) boot: Enabling RNG early entropy source… I (61) boot: Partition Table: I (64) boot: ## Label Usage Type ST Offset Length I (72) boot: 0 nvs WiFi data 01 02 00009000 00006000 I (79) boot: 1 phy_init RF data 01 01 0000f000 00001000 I (87) boot: 2 factory factory app 00 00 00010000 00100000 I (94) boot: End of partition table I (98) boot_comm: chip revision: 1, min. application chip revision: 0 I (105) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x02eb8 ( 11960) map I (120) esp_image: segment 1: paddr=0x00012ee0 vaddr=0x3ffbae40 size=0x0006c ( 108) load I (123) esp_image: segment 2: paddr=0x00012f54 vaddr=0x40080000 size=0x00400 ( 1024) load I (133) esp_image: segment 3: paddr=0x0001335c vaddr=0x40080400 size=0x01c64 ( 7268) load I (145) esp_image: segment 4: paddr=0x00014fc8 vaddr=0x00000000 size=0x0b050 ( 45136) I (169) esp_image: segment 5: paddr=0x00020020 vaddr=0x400d0020 size=0x1a43c (107580) map I (217) boot: Loaded app from partition at offset 0x10000 I (218) boot: Disabling RNG early entropy source… NuttShell (NSH) NuttX-9.1.0 nsh> free total used free largest Umem: 4477264 15872 4461392 4194288 nsh> ? help usage: help [-v] [] . cd exec ifconfig mkrd put test usleep [ cp exit ifdown mh pwd telnetd wget ? cmp false ifup mount rm time xd arp dirname free kill mv rmdir true basename dd get ls mw set uname break df help mb nslookup sleep umount cat echo hexdump mkdir ps source unset Builtin Apps: sh ramtest ping nsh nsh> ramtest -w 0x3F800000 4194304 RAMTest: Marching ones: 3f800000 4194304 RAMTest: Marching zeroes: 3f800000 4194304 RAMTest: Pattern test: 3f800000 4194304 55555555 aaaaaaaa RAMTest: Pattern test: 3f800000 4194304 66666666 99999999 RAMTest: Pattern test: 3f800000 4194304 33333333 cccccccc RAMTest: Address-in-address test: 3f800000 4194304 nsh>
Some time ago I needed to link with ARM DSP library on NuttX to use FFT feature and I decided to document who I did it and some tricks to reduce the final binary size.
In fact to include a library all you need to do is add it to your board Make.defs. See a simple patch file to stm32f4discovery:
index 59aa60bf6b..5e6845c81c 100644 --- a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs +++ b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs @@ -63,6 +63,8 @@ CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) AFLAGS = $(CFLAGS) -D__ASSEMBLY__ +EXTRA_LIBS = "$(TOPDIR)/3rparty/libarmdsp.a" + NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections LDNXFLATFLAGS = -e main -s 2048
It means you need to create a “3rdpary” directory at root of nuttx/ and put your library there.
But after the compilation you will notice that your nuttx.bin binary will become very big. It happens because the linker will include all the functions in the library.
You can instruct it to include only the needed functions using this parameter with LDFLAGS:
LDFLAGS += --gc-sections
Now your binary will become way smaller
If you decide you create your own NuttX application based on apps/examples/hello you could eventually face this issue:
CC: my_app_main.c
:0:6: error: expected identifier or '(' before numeric constant
:0:6: error: expected identifier or '(' before numeric constant
my_app_main.c:51:5: note: in expansion of macro 'main'
int main(int argc, FAR char *argv[])
^
make[3]: *** [/home/alan/apps/Application.mk:189: my_app_main.home.alan.apps.examples.my_app.o] Error 1
This error happens because your PROGNAME defined inside the Kconfig differs from your application name:
config EXAMPLES_MYAPPNAME_PROGNAME
string "Program name"
default "myapp"
If your PROGNAME is myapp then you need to have apps/examples/myapp/myapp_main.c otherwise it will not work. So don’t my_app for your app directory neither my_app_main.c for your main file, it needs to be myapp_main.c
These researchers suggested using Chitin protein to create structures in Mars:
https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7494075/
If you want to try, the instruction to get this protein is here:
Let’s save this link: